# “A heisenbug (named after the Heisenberg Uncertainty Principle) is a computer bug that disappears or alters its characteristics when an attempt is made to study it.”

## Why do we perform small signal analysis?

Why do we perform small signal analysis, when we are analyzing or designing analog circuits? This is a fundamental question that I think, is not discussed rigorously enough in the classes or text books on analog circuit design. I will attempt to qualitatively address this question here in this blogpost. Fig. 1 a) Small-signal MOSFET model and b) small-signal bipolar model

The way we derive the small signal models for transistors (shown in Fig. 1 a) and b) ) tells us something about the answer to the question i.e. by using the methods to describe transistors with their small-signal models, we can reduce the non-linear devices (like MOSFETs, bipolar transistors and diodes) to a circuit composed of linear elements. A circuit described by linear elements is much easier to analyze, also it provides us some handle to the circuit which we can use for the problem of design. Moreover, we can’t really perform a complete SPICE like analysis on paper by hand.

Another way to look at it, as professor Razavi has described in the third chapter of his widely studied textbook, even if the amplifier has a non-linear response, its response can be captured by a polynomial function in a certain signal range. For small-signals the polynomial response function reduces to a constant or in other words the response is linear.

The answer I provided above sounds pedantic and it also leads to another question – how and why is small signal analysis valid? and why is it not just a method of abstraction for easier analysis? For example and as shown in the Fig. 2, the signals applied between nodes A, B, C and ground are not necessarily small and they can in the order of volts or larger. So, is the small-signal analysis valid for the amplifiers I, II and III? If yes, why?

Fig. 2 Typical use of amplifiers

The short answer to the second question is – yes and the reason is negative feedback. Another academic sounding answer. Allow me to me elaborate and lets assume that the amplifiers I, II and III shown in Fig 2. are the well known single-ended two-stage CMOS amplifier shown in Fig. 3. The amplifier (opamp) doesn’t necessarily have to be a two-stage CMOS amplifier, but more or less similar behavior is demonstrated by the other amplifiers as well. Fig. 3  Two-stage CMOS amplifier

Fig. 4 circuit from fig. 2 top left redrawn

Lets start with the circuit in Fig 2 top left, redrawn in Fig 4. For the sake of this discussion I will assume that the resistors R1 and R2 are very large and equal. The resistors R1 and R2 have to be large so that they don’t draw too much current out of the 2nd stage of the amplifier (current drawn by the resistors should be less than 10 % of 2nd-stage the bias current for ?n,p ? 0.1 or VEarly n,p ? 10 V). Let me also assume that VDD and VSS are +3 V and -3V, respectively.  We now apply a signal (Vin) of 1 Volt at node A, as a result some current flows through R1 and it will result in a voltage Vn at the negative terminal of the amplifier (the gate of transistor M2). If voltage Vn is positive, the voltage on node D1 will go up causing the transistor M6 to become less ON and resulting the output voltage of the amplifier to go low somewhere close to VSS. Similarly if the voltage Vn is negative, the voltage on node D2 will go down causing the transistor to become more ON and resulting in the amplifier output to go up somewhere close to VDD. Now in this particular case the voltage Vn can not be a negative voltage, as that will result in currents through R1 and R2 to flow into node n, which is not possible according to Kirchoff’s current law.

Since we don’t know what the voltage at the input (Vn) looks like and if it is not a small signal it will tend to turn transistor M2 considerably more ON and almost turn M1 OFF, as a result the node D1 will be pulled high, close to VDD rail. The transistor M6 will be close to being OFF and the output is likely to be VSS rail. In that case the voltage at the node n, using the resistive divider equation, will be (Vin x R2 + VSS x R1)/(R2 + R1) = (R x 1 + R x -3) / (R + R) = -2. Now, a negative voltage on n will tend to pull the output away from VSS rail and thus, as we discussed earlier, it is not a possible stable voltage on the negative input terminal (node n). In fact, the voltage on the negative terminal of the amplifier has to be R2/R1 x Vin/A (algebra below)

where A is the voltage gain of the amplifier (whatever that maybe). If every FET in the amplifier discussed above is operating in saturation the voltage gain A of the circuit will be large. So the voltage at node n will be a small number, so the input to the amplifier is a small voltage i.e. a small signal.

Similarly, for the circuit of top right when a large positive voltage is applied on the positive terminal (B) of the amplifier, its output tends to swing up. Amplifier’s output continues to swing up to a level which is just below Vin, such that the difference between Vin and Vout is small enough to cause amplifier output to stop being pulled to the VDD rail. In other words A(Vin – Vout) = Vout or Vout = Vin x (A / (1 + A)). Therefore the input voltage between two terminals of the amplifier Vin – Vout = Vin/(1 + A), when A is large (100 or larger is good enough in most cases) the signal seen by the amplifier is small.

For the circuit shown in bottom center of Fig. 2 redrawn in Fig. 5 below, when we apply a voltage Vin at node C, some charge q1 develops on the top plate of capacitor C1, now equivalent negative charge has to appear on the bottom plate of capacitor C1. The charge developed on the bottom plate has to be balanced by a positive charge on the negative terminal (n) of the amplifier. A positive charge on the negative input of the amplifier will imply a positive voltage on the negative terminal of the amplifier and a positive voltage on the negative terminal of amplifier will cause the amplifier output to go low, towards VSS rail. Now capacitor C2 will start accumulating negative charge on the plate connected to the amplifier output, to balance that negative charge some positive charge (which was generated by the act of applying a voltage Vin on C1, in first place) from the negative terminal of the amplifier will get transferred to the bottom plate of capacitor C2. The transfer of charge will take place until a stable voltage Vn develops on the negative terminal of the amplifier resulting in a stable output voltage Vout. According to conservation of charge + q1 on top plate of C1 = – q1 on the bottom plate of C1, – q1 gets balanced by total positive charge on bottom plate of C2 and the negative terminal of the amplifier. q1 = C1(Vin – Vn) = – C2(Vout – Vn) + Cp,amp x Vn. Cp,amp is the parasitic capacitance at the negative terminal of the amplifier, also Vn = – Vout / A. Substituting in the equation we get Vout = – C1 / ( C2 + (C1 + C2 + Cp,amp) / A) x Vin ? – C1 / C2 x Vin for large A, therefore Vn = – C1 / C2 x Vin / A, which is small for large A.

Fig. 5 redrawn switched capacitor circuit from Fig. 2

Small signals at input are all good, how about the signals at output? The output signals in all the circuits discussed above are not small, again. However, MOSFETs and BJTs both have an interesting property of linear current (ID or IC) vs voltage relationships (at the drain and collector terminals) for a very wide voltage range (voltages ~ supply voltages), when operated in saturation and forward active regions. This is illustrated in the Fig. 5 below. The small signal parameter ro can practically capture the behavior of the devices for large voltage signals.

Fig. 6 ID – VD and IC – VC curves

All the circuits discussed above are using amplifier in a closed loop, however not all analog circuits are used in a closed loop, the sginal for those circuits may not necessarily be small all the time. For circuits such as comparator, LNA, mixers or power amplifiers, the small signal analysis is not valid entirely, it is just an approximate engineering method used to simplify the analysis. In the case of RF circuits, the linearity is essentially simulated/estimated using the CAD tools and that is why qualifications for RF circuit design requires understanding of the limitations of simulators and models in estimating linearity and high frequency behavior of circuits in addition to all high frequency circuit design theory.

This blog is intended for people starting to learn analog circuit design, however it still requires some familiarity with somewhat advanced (from a beginner’s standpoint) analog circuits such as differential amplifiers. It becomes much easier to learn circuit design if we can understand how and why the methodologies for analyzing circuits are applicable to the actual circuits.

If you notice any mistake or have any suggestion for adding anything here, please email me at achal[ dot ]kathuria[ at ]gmail. I will sincerely appreciate any feedback.

Originally posted at – http://analogcircuits.posterous.com/50674697 not a person of conventional wisdom

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### One Response

1. Amlan says: